Static random access memory (SRAM) memory cells retain their memory states as long as power is supplied to the memory cells. A conventional SRAM memory cell for a single-port memory includes a pair of cross-coupled inverters and corresponding pair of access transistors. Because an inverter requires at least two transistors (a serial stack of a PMOS transistor and an NMOS transistor), a conventional SRAM single-port memory cell uses six transistors.
In contrast, a dynamic random access memory (DRAM) uses a one-transistor memory cells such that a DRAM offers considerable density advantages and is thus cheaper than SRAM. But the cross-coupled inverters in an SRAM drive the stored memory content onto the bit lines whereas a DRAM has no such active drive. Thus, SRAM is typically much faster than DRAM such that SRAM is reserved for time-critical operations such as memory caches.
The greater cost of SRAM is exacerbated in multi-port applications because each additional port is conventionally accommodated at the memory cell level by an additional pair of access transistors. Thus, a conventional dual-port memory cell requires eight transistors, a three-port memory cell requires ten transistors, and so on. These additional transistor demand die space and increase the resulting cost of the SRAM.
Accordingly, there is a need in the art for multi-port SRAMs with enhanced densities.